Segment descriptor reference

upper dword																																lower dword																																Download PDF
6 3	6 2	6 1	6 0	5 9	5 8	5 7	5 6	5 5	5 4	5 3	5 2	5 1	5 0	4 9	4 8	4 7	4 6	4 5	4 4	4 3	4 2	4 1	4 0	3 9	3 8	3 7	3 6	3 5	3 4	3 3	3 2	3 1	3 0	2 9	2 8	2 7	2 6	2 5	2 4	2 3	2 2	2 1	2 0	1 9	1 8	1 7	1 6	1 5	1 4	1 3	1 2	1 1	1 0	9	8	7	6	5	4	3	2	1	0	bit offset
Base 31:24								G	D B	L	⋰	Limit 19:16				P	DPL		S	Type				Base 23:00																								Limit 15:00																General format
Base 31:24								G	B	0	⋰	Limit 19:16				P	DPL		1	0	E	W	A	Base 23:00																								Limit 15:00																Data Segment
Base 31:24								G	D	0	⋰	Limit 19:16				P	DPL		1	1	C	R	A	Base 23:00																								Limit 15:00																Code Segment (16-/32-bit)
Reserved								G	D	1	⋰	Reserved				P	DPL		1	1	C	R	A	Reserved																																								Code Segment (IA-32e)
Base 31:24								G	R	0	R	Limit 19:16				P	DPL		0	Type				Base 23:00																								Limit 15:00																System Segment
Offset in Segment 31:16																P	DPL		0	1100				0	0	0	Param count					Segment selector																Offset in Segment 15:00																Call Gate (32-bit)
Offset in Segment 31:16																P	DPL		0	1100				0	0	0	0	0	0	0	0	Segment selector																Offset in Segment 15:00																Call Gate (IA-32e)
Reserved																				0000				Reserved								Offset in Segment 63:31																																64-bit Call Gate extension (at 8 byte offset)
Offset in Segment 31:16																P	DPL		0	D	1	1	0	0	0	0	Reserved					Segment selector																Offset in Segment 15:00																Interrupt Gate
Offset in Segment 31:16																P	DPL		0	D	1	1	1	0	0	0	Reserved					Segment selector																Offset in Segment 15:00																Trap Gate
Reserved																P	DPL		0	D	1	0	1	Reserved								TSS Segment selector																Reserved																Task Gate
Base 31:24								G	0	0	⋰	Limit 19:16				P	DPL		0	Type				Base 23:00																								Limit 15:00																TSS/LDT Descriptor

A bit

Segment was Accessed

B bit

Big data segment. (For code segments, see the D bit.)

For stack segment (when pointed to by %ss):: Use the 32-bit stack pointer %esp when set to 1. Use the 16-bit stack pointer %sp otherwise.
For expand-down segments:: When set, the upper bound is 0xffffffff (4 GiB). The upper bound is 0xffff (64 KiB) otherwise.

C bit

Conforming.

D bit (code segment)

Use 32-bit addresses and 32-/8-bit operands when set. Use 16-bit addesses and operands otherwise.

Overriden by the instruction prefixes 0x66 and 0x67.

For behavior for data segments, see the B bit.

D/B bit

See the D and B bits above.

E bit

Expand-down segment.

G bit

Granularity. When set, the Limit is in 4KiB units. (It's in 1Byte units otherwise.

L bit

Long-mode flag.

P bit

Present.

R bit (code segments)

Readable. (For data segments, see the W bit.

S bit

W bit (data segments)

Writable. (For code segments, see the R bit.

DPL

Descriptor Privilege Level.

⋰ (AVL in Intel docs)

Available for program use.

Upper Type bit (for non-system segments)

It's 1 for code and 0 for data. (The SDM forgets to mention this explicitly AFAIK.)

Descriptor types

Segment descriptor type table from the SDM (Data, Code, System)

Type						Description
dec	hex	bin
dec	hex	8	4	2	1
		?	E	W	A	Data segment
0	0	0	0	0	0	Data	Read-Only
1	1	0	0	0	1	Data	Read-Only		Accessed
2	2	0	0	1	0	Data	Read/Write
3	3	0	0	1	1	Data	Read/Write		Accessed
4	4	0	1	0	0	Data	Read-Only	Expand-down
5	5	0	1	0	1	Data	Read-Only	Expand-down	Accessed
6	6	0	1	1	0	Data	Read/Write	Expand-down
7	7	0	1	1	1	Data	Read/Write	Expand-down	Accessed
		?	C	R	A	Code segment
8	8	1	0	0	0	Code	Execute-Only
9	9	1	0	0	1	Code	Execute-Only		Accessed
10	a	1	0	1	0	Code	Execute/Read
11	b	1	0	1	1	Code	Execute/Read		Accessed
12	c	1	1	0	0	Code	Execute-Only	Conforming
13	d	1	1	0	1	Code	Execute-Only	Conforming	Accessed
14	e	1	1	1	0	Code	Execute/Read	Conforming
15	f	1	1	1	1	Code	Execute/Read	Conforming	Accessed
		¿				System Segment
		¿				32-bit Mode		IA-32e Mode
0	0	0	0	0	0	Reserved		Reserved (extension of descriptor to 64 bits)
1	1	0	0	0	1	16-bit TSS	Available	Reserved
2	2	0	0	1	0	LDT
3	3	0	0	1	1	16-bit TSS	Busy	Reserved
4	4	0	1	0	0	16-bit Call Gate		Reserved
5	5	0	1	0	1	Task Gate		Reserved
6	6	0	1	1	0	16-bit Interrupt Gate		Reserved
7	7	0	1	1	1	16-bit Trap Gate		Reserved
8	8	1	0	0	0	Reserved		Reserved
9	9	1	0	0	1	32-bit TSS	Available	64-bit TSS	Available
10	a	1	0	1	0	Reserved
11	b	1	0	1	1	32-bit TSS	Busy	64-bit TSS	Busy
12	c	1	1	0	0	32-bit Call Gate		64-bit Call Gate
13	d	1	1	0	1	Reserved		Reserved
14	e	1	1	1	0	32-bit Interrupt Gate		64-bit Interrupt Gate
15	f	1	1	1	1	32-bit Trap Gate		64-bit Trap Gate

Segment descriptor type table when treating the S bit as a part of the type

Type							Description
dec	hex	bin
dec	hex	16	8	4	2	1
		S	?	E	W	A	Data segment
0	00	0	0	0	0	0	Data	Read-Only
1	01	0	0	0	0	1	Data	Read-Only		Accessed
2	02	0	0	0	1	0	Data	Read/Write
3	03	0	0	0	1	1	Data	Read/Write		Accessed
4	04	0	0	1	0	0	Data	Read-Only	Expand-down
5	05	0	0	1	0	1	Data	Read-Only	Expand-down	Accessed
6	06	0	0	1	1	0	Data	Read/Write	Expand-down
7	07	0	0	1	1	1	Data	Read/Write	Expand-down	Accessed
		S	?	C	R	A	Code segment
8	08	0	1	0	0	0	Code	Execute-Only
9	09	0	1	0	0	1	Code	Execute-Only		Accessed
10	0A	0	1	0	1	0	Code	Execute/Read
11	0B	0	1	0	1	1	Code	Execute/Read		Accessed
12	0C	0	1	1	0	0	Code	Execute-Only	Conforming
13	0D	0	1	1	0	1	Code	Execute-Only	Conforming	Accessed
14	0E	0	1	1	1	0	Code	Execute/Read	Conforming
15	0F	0	1	1	1	1	Code	Execute/Read	Conforming	Accessed
		S	¿				System Segment
		S	¿				32-bit Mode		IA-32e Mode
16	10	1	0	0	0	0	Reserved		Reserved (extension of descriptor to 64 bits)
17	11	1	0	0	0	1	16-bit TSS	Available	Reserved
18	12	1	0	0	1	0	LDT
19	13	1	0	0	1	1	16-bit TSS	Busy	Reserved
20	14	1	0	1	0	0	16-bit Call Gate		Reserved
21	15	1	0	1	0	1	Task Gate		Reserved
22	16	1	0	1	1	0	16-bit Interrupt Gate		Reserved
23	17	1	0	1	1	1	16-bit Trap Gate		Reserved
24	18	1	1	0	0	0	Reserved		Reserved
25	19	1	1	0	0	1	32-bit TSS	Available	64-bit TSS	Available
26	1A	1	1	0	1	0	Reserved
27	1B	1	1	0	1	1	32-bit TSS	Busy	64-bit TSS	Busy
28	1C	1	1	1	0	0	32-bit Call Gate		64-bit Call Gate
29	1D	1	1	1	0	1	Reserved		Reserved
30	1E	1	1	1	1	0	32-bit Interrupt Gate		64-bit Interrupt Gate
31	1F	1	1	1	1	1	32-bit Trap Gate		64-bit Trap Gate

Chapters of the Intel® SDM with more useful info:

Vol. 3, chapter 3: Protected-Mode Memory Management
Vol. 3, chapter 5: Protection

This page might contain incomplete or incorrect information. Please refer to the Intel® 64 and IA-32 Architectures Software Developer's Manual. You can find more resources at x86asm.net.

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Created: July 2026